1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and specifically relates to a semiconductor device, in which a transistor for a nonvolatile memory cell having a floating gate electrode and a control electrode and a transistor for a peripheral circuit are mounted in a mixed manner on the same substrate, and a method for manufacturing the semiconductor device.
2. Description of the Related Art
A semiconductor device includes a nonvolatile semiconductor storage device called a flash memory. In general flash memories, as disclosed in Jpn. Pat. Appln. KOKAI Publication No. 2002-176114 for example, a transistor for a nonvolatile memory cell, which has two gate electrodes, one of which is a floating gate electrode as a lower gate electrode, and the other of which is a control gate electrode as an upper gate electrode, and a transistor for a peripheral circuit having the same structure as the transistor for a nonvolatile memory cell are mounted in a mixed manner on the same silicon substrate. The transistor for a nonvolatile memory cell and the transistor for a peripheral circuit are normally formed in parallel by substantially the same process, and have a structure in which an insulating film is put between a floating gate electrode composed of a polysilicon layer and a control gate electrode. In some transistors in the memory cell part and the peripheral circuit part, in order to electrically connect a polysilicon layer (FG poly-Si layer) as the floating gate electrode with a polysilicon layer (CG poly-Si layer) as the control gate electrode, an opening through which the FG poly-Si layer is exposed is formed so as to penetrate through a part of an insulating film on the FG poly-Si layer by etching.
Recently, the demand for improvement of the write speed of the memory cell with the miniaturization of the flash memory is increased. The FG poly-Si layer should be formed thinner for this demand. The opening formed in the transistor in the peripheral circuit part normally has an opening area larger than the opening formed in a selection transistor in the memory cell part, whereby the etching amount (depth) of the FG poly-Si layer in the formation of the opening in the peripheral circuit part is larger than that in the memory cell part. Therefore, if the thickness (Tperi) of the FG poly-Si layer in the peripheral circuit part is reduced so as to be equivalent to the thickness (Tcell) of the FG poly-Si layer in the memory cell part, the opening part in the peripheral circuit part penetrates through the FG poly-Si layer to reach the inside of the silicon substrate, whereby there arises a problem that short circuiting occurs between the gate electrode and the Si substrate when a contact conducting film is buried in the opening. Additionally, in the peripheral circuit part, since the FG poly-Si layer is used as a resistance element, there is also a problem that an intended resistance value cannot be secured due to the thickness reduction of the FG poly-Si layer. Further, in order to avoid the above problems, a process for individually forming the FG poly-Si layer and the opening in each of the memory cell part and the peripheral circuit part is considered; however, there arises a problem of increasing the process steps to lower the productivity.